RISC architecture
A processor with RISC (reduced instruction set computer) architecture, i.e. with a reduced instruction set, has the following features:
- it is built according to the Harvard-type architecture, so it has separate buses for data and program, so it can work with data and program memory at the same time,
- uses pipelining to increase program execution speed,
- the set of implemented instructions is limited and meets the orthogonality conditions.
The concept of orthogonality means the unification of instructions according to the following principles:
- each instruction can operate on any working register, so the processor does not have specific registers that are specialized to perform specific types of operations,
- each instruction can use any argument addressing mode,
- there are no hidden connections between instructions (side effects) that would cause unexpected system reactions depending on the context of using the instructions in the program,
- instruction codes and instruction formats are unified, in particular, all instructions occupy the same number of bytes in program memory.
The orthogonality of the instruction set radically simplifies the construction of a control system that can implement the execution cycle of each instruction according to an identical algorithm. Moreover, a simpler control system can work much faster, therefore the command cycle is shortened. The saved area on the chip is used for additional blocks, such as the hardware stack, which further speed up the processor.
The opposite of the RISC architecture is the CISC (complex instruction set computer) architecture. Processors of this type have an extensive instruction list, often including several hundred different commands. The orthogonality of instructions is not preserved, instructions are narrowly specialized, generally work only with specific registers and require the use of specific addressing modes. The abundance of instruction lists and addressing modes makes it difficult for a programmer to master the assembly language, but it facilitates writing compact source programs.
The SU 1.2 and SU 1.5 controllers use 8-bit microcontrollers with the RISC architecture from ATMEL.
In these processors, the use of program pipeline processing means that simultaneously (in one clock cycle) a given instruction is executed and the next instruction is downloaded from code memory.
Because AVR microcontrollers execute most instructions within a single clock cycle, these chips can achieve processing speeds of up to 1 MIPS per 1 MHz of crystal resonator.